I. Field of the Disclosure
The technology of the disclosure relates generally to magnetic tunnel junctions (MTJs), and more particularly to MTJs employed in magnetic random access memory (MRAM) bit cells to provide MRAM.
II. Background
Semiconductor storage devices are used in integrated circuits (ICs) in electronic devices to provide data storage. One example of a semiconductor storage device is magnetic random access memory (MRAM). MRAM is non-volatile memory in which data is stored by programming a magnetic tunnel junction (MTJ) as part of an MRAM bit cell. One advantage of an MRAM is that MTJs in MRAM bit cells can retain stored information even when power is turned off. This is because data is stored in the MTJs as a small magnetic element rather than as an electric charge or current.
In this regard, an MTJ comprises a free ferromagnetic layer (“free layer”) disposed above a fixed or pinned ferromagnetic layer (“pinned layer”). The free and pinned layers are formed from a ferromagnetic material either with perpendicular magnetic anisotropy (i.e., the magnetization direction is perpendicular to a layer plane) to form a perpendicular MTJ (pMTJ), or with in-plane magnetic anisotropy to form an in-plane MTJ. The free and pinned layers are separated by a tunnel junction or barrier formed by a thin non-magnetic dielectric layer. The magnetic orientation of the free layer can be changed, but the magnetic orientation of the pinned layer remains fixed or “pinned.” Data can be stored in the MTJ according to the magnetic orientation between the free and pinned layers. When the magnetic orientations of the free and pinned layers are anti-parallel (AP) to each other, a first memory state exists (e.g., a logical ‘1’). When the magnetic orientations of the free and pinned layers are parallel (P) to each other, a second memory state exists. The magnetic orientations of the free and pinned layers can be sensed to read data stored in the MTJ by sensing a resistance when current flows through the MTJ. Data can also be written and stored in the MTJ by applying a magnetic field to change the magnetic orientation of the free layer to either a P or AP magnetic orientation with respect to the pinned layer.
Recent developments in MTJ devices involve spin transfer torque (STT)-MRAM devices. In STT-MRAM devices, the spin polarization of electrons, rather than the local magnetic fields, is used to program the state stored in the MTJ (i.e., a ‘0’ or a ‘1’). In this regard, FIG. 1 illustrates a STT-MTJ 100. The STT-MTJ 100 is provided as part of an MTJ memory bit cell 102 to store non-volatile data. A metal-oxide semiconductor (MOS) (typically n-type MOS, i.e., NMOS) access transistor 104 is provided to control reading and writing to the STT-MTJ 100. A drain node (D) of the access transistor 104 is coupled to a bottom electrode 106 of the STT-MTJ 100, which is coupled to a pinned layer 108. A word line (WL) is coupled to a gate node (G) of the access transistor 104. A source node (S) of the access transistor 104 is coupled to a voltage source (VS) through a source line (SL). The voltage source (VS) provides a voltage (VSL) on the source line (SL). A bit line (BL) is coupled to a top electrode 110 of the STT-MTJ 100, which is coupled to a free layer 112. The pinned layer 108 and the free layer 112 are separated by a tunnel barrier 114.
With continuing reference to FIG. 1, when writing data to the STT-MTJ 100, the gate node (G) of the access transistor 104 is activated by activating the word line (WL). A voltage differential between a voltage (VBL) on the bit line (BL) and the voltage (VSL) on the source line (SL) is applied. As a result, a write current (I) is generated between the drain node (D) and the source node (S) of the access transistor 104. If the magnetic orientation of the STT-MTJ 100 in FIG. 1 is to be changed from AP to P, a write current (IAP-P) flowing from the top electrode 110 to the bottom electrode 106 is generated. This induces a spin transfer torque (STT) at the free layer 112 to change the magnetic orientation of the free layer 112 to P with respect to the pinned layer 108. If the magnetic orientation is to be changed from P to AP, a current (IP-AP) flowing from the bottom electrode 106 to the top electrode 110 is produced, which induces an STT at the free layer 112 to change the magnetic orientation of the free layer 112 to AP with respect to the pinned layer 108.
With continuing reference to FIG. 1, the write current (I) required to be generated between the bit line (BL) and the source line (SL) of the MTJ memory bit cell 102 may be fifty (50) to one hundred (100) micro-Amps (μA) as an example. As fabrication processes allow nodes to be further scaled down in size to reduce area for a given chip or package size, metal interconnection resistance increases due to the reduced cross-sectional area available for metal interconnects in the chip. Thus for example, if the size of the MTJ memory bit cell 102 in FIG. 1 is maintained in a given chip or package as node size is scaled down, the amount of write current (I) generated across the STT-MTJ 100 will drop due to the increased resistance in the bit line (BL) and the source line (SL) for a given voltage source (VS) level (i.e., write current (I)=(VSL−VBL)/resistance). Thus, the write current (I) margin is reduced, which can lead to reduced write performance of the MTJ memory bit cell 102 and yield loss. To solve the issue of increased resistance in the MTJ memory bit cell 102 from node size down scaling, the voltage (VSL) supplied by the voltage source (VS) can be increased to maintain the write current (I) to a required current level necessary to perform write operations in the MTJ memory bit cell 102. However, increasing the voltage (VSL) of the voltage source (VS) increases power consumption, which may be undesirable. Also, in many chip designs, it may not be possible to increase the voltage (VSL) of the voltage source (VS), because the voltage source (VS) is reduced in accordance with general semiconductor technology scaling, for example, to maintain gate dielectric integrity and to reduce overall power consumption in the chip.